IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 342

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–36
Table B–17. Sideband Signals
PCI Express Compiler User Guide
app_int_sts_icm
cfg_busdev_icm
cfg_devcsr_icm
cfg_linkcsr_icm
cfg_tcvcmap_icm
cpl_err_icm
pex_msi_num_icm
cpl_pending_icm
app_int_sts_ack_ic
m
cfg_msicsr_icm
test_out_icm
Notes to
(1) Refer to
(2) Refer to
(3) Refer to
Table
Signal
Table B–11 on page
Table 5–17 on page 5–39
Table 5–9 on page 5–29
B–17:
Sideband Interface
Table B–17
[8:0]
[4:0]
[8:5]
Bit
—
—
—
—
—
—
—
—
—
—
B–25f or more information.
for more information.
for more information.
Same as app_int_sts on the IP core interface. ICM delays this signal by one clock.
Delayed version of cfg_busdev on the IP core interface.
Delayed version of cfg_devcsr on the IP core interface.
Delayed version of cfg_linkcsr on IP core interface. ICM delays this signal by one
clock.
Delayed version of cfg_tcvcmap on IP core interface.
Same as cpl_err_icm on IP core interface (1). ICM delays this signal by one clock.
Same as pex_msi_num on IP core interface (3). ICM delays this signal by one clock.
Same as cpl_pending on IP core interface (1). ICM delays this signal by one clock.
clock. This signal applies to the ×1 and ×4 IP cores only. In ×8, this signal is tied low.
clock.
This is a subset of test_out signals from the IP core. Refer to
description of test_out.
“ltssm_r” debug signal. Delayed version of test_out[4:0] on ×8 IP core interface.
Delayed version of test_out[324:320] on ×4/ ×1 IP core interface.
“lane_act” debug signal. Delayed version of test_out[91:88] on ×8 IP core interface.
Delayed version of test_out[411:408] on ×4/ ×1 IP core interface.
Delayed version of app_int_sts_ack on IP core interface. ICM delays this by one
Delayed version of cfg_msicsr on the IP core interface. ICM delays this signal by one
describes the application-side sideband signals.
(2)
Description
Recommended Incremental Compilation Flow
(2)
(2)
(2)
December 2010 Altera Corporation
Appendix B
for a
Chapter :
(3)