IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 23

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: Datasheet
Recommended Speed Grades
Recommended Speed Grades
December 2010 Altera Corporation
f
Table 1–8
the Avalon-ST or Avalon-MM interface with a maximum payload of 256 bytes and 32
tags for the Avalon-ST interface and 16 tags for the Avalon-MM interface.
Table 1–8. Performance and Resource Utilization in Arria II GX, Arria II GZ, Cyclone IV GX,
Stratix IV GX, and Stratix V GX Devices
Refer to
for performance and resource utilization for the soft IP implementation.
Table 1–9
supported link widths and internal clock frequencies. For soft IP implementations of
the PCI Express IP core, the table lists speed grades that are likely to meet timing; it
may be possible to close timing in a slower speed grade. For the hard IP
implementation, the speed grades listed are the only speed grades that close timing.
When the internal clock frequency is 125 MHz or 250 MHz, Altera recommends
setting the Quartus II Analysis & Synthesis Settings Optimization Technique to
Speed.
Note to
(1) The transaction layer of the Avalon-MM implementation is implemented in programmable logic to improve latency.
Width
Lane
×1
×1
×4
×4
×8
×8
×1
×4
×1
×4
Table
Appendix C, Performance and Resource Utilization Soft IP Implementation
Avalon-MM Interface–SOPC Builder Design Flow - Completer Only Single Dword
Clock (MHz)
shows the resource utilization for the hard IP implementation using either
shows the recommended speed grades for each device family for the
Parameters
Internal
1–8:
125
125
125
125
250
250
125
125
125
125
Avalon-ST Interface–MegaWizard Plug-In Manager Design Flow
Avalon-MM Interface–SOPC Builder Design Flow
Channel
Virtual
1
2
1
2
1
2
1
1
1
1
Combinational
ALUTs
4300
4200
100
100
200
200
200
200
250
250
Dedicated
Registers
3500
3400
100
100
200
200
200
200
230
230
Size
PCI Express Compiler User Guide
(1)
Memory Blocks
M9K
17
17
0
0
0
0
0
0
0
0
1–13