IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 98

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–14
Table 5–4. 64-, 128-, or 256-Bit Avalon-ST TX Datapath (Part 2 of 5)
PCI Express Compiler User Guide
tx_st_valid<n>
(continued)
tx_st_valid<n>
tx_st_data<n>
tx_st_sop<n>
tx_st_eop<n>
tx_st_empty<n>
tx_st_err<n>
tx_fifo_full<n>
tx_fifo_empty<n>
Signal
(2)
1
64,
128,
256
1
1
1
1
1
1
Width Dir
I
I
I
I
I
I
O
O
Component Specific Signals
valid
data
start of
packet
end of
packet
empty
error
component
specific
component
specific
Avalon-ST
Type
implementation. When tx_st_ready<n> reasserts, and
tx_st_data<n> is in mid-TLP, this signal must reassert
within 3 cycles for soft IP and 2 cycles for the hard IP
implementation. Refer to
the timing of this signal.
To facilitate timing closure, Altera recommends that you
register both the tx_st_ready and tx_st_valid
signals. If no other delays are added to the ready-valid
latency, this corresponds to a readyLatency of 2
Data for transmission.Transmit data bus. Refer to
Figure 5–17
packets to tx_st_data<n>. Refer to
timing of this interface. When using a 64-bit Avalon-ST
bus, the width of tx_st_data is 64. When using 128-bit
Avalon-ST bus, the width of tx_st_data is 128. When
using the 256-bit Avalon-ST bus, the width of
tx_st_data is 256 bits. The application layer must
provide a properly formatted TLP on the TX interface. The
mapping of message TLPs is the same as the mapping of
transaction layer TLPs with 4 dword headers. The number
of data cycles must be correct for the length and address
fields in the header. Issuing a packet with an incorrect
number of data cycles results in the TX interface hanging
and unable to accept further requests.
Indicates first cycle of a TLP.
Indicates last cycle of a TLP.
Indicates that the TLP ends in the lower 64 bits of
tx_st_data<n>. Valid only when tx_st_eop<n> is
asserted.This signal only applies to 128-bit mode in the
hard IP implementation.
Indicates an error on transmitted TLP. This signal is used
to nullify a packet. It should only be applied to posted and
completion TLPs with payload. To nullify a packet, assert
this signal for 1 cycle after the SOP and before the EOP.
In the case that a packet is nullified, the following packet
should not be transmitted until the next clock cycle. This
signal is not available on the ×8 Soft IP. tx_st_err is not
available for packets that are 1 or 2 cycles long.
Refer to
that illustrates the use of the error signal. Note that it
must be asserted while the valid signal is asserted.
Indicates that the adapter TX FIFO is almost full. Does not
apply to Stratix V devices.
Indicates that the adapter TX FIFO is empty.Does not
apply to Stratix V devices.
Figure 5–20 on page 5–19
through
Figure 5–22
Description
Figure 5–25 on page 5–22
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
for the mapping of TLP
for a timing diagram
Figure 5–25
Avalon-ST Interface
for the
for