IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 50

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–8
Table 3–3. Capabilities Parameters (Part 2 of 4)
PCI Express Compiler User Guide
Implement
advanced error
reporting
Parity
MSI messages
requested
Completion
timeout range
(continued)
Implement ECRC
check
Implement ECRC
generation
Implement ECRC
forwarding
MSI message
64–bit address
capable
Parameter
On/Off
On/Off
On/Off
On/Off
On/Off
1, 2, 4, 8,
16, 32
On/Off
Value
This setting is not available for PCIe version 1.0. All other values are reserved. Altera
recommends that the completion timeout mechanism expire in no less than 10 ms.
Implements the advanced error reporting (AER) capability.
Enables ECRC checking capability. Sets the read-only value of the ECRC check
capable bit in the advanced error capabilities and control register. This parameter
requires you to implement the advanced error reporting capability.
Enables ECRC generation capability. Sets the read-only value of the ECRC generation
capable bit in the advanced error capabilities and control register. This parameter
requires you to implement the advanced error reporting capability.
Available for hard IP implementation only. Forward ECRC to the application layer. On
the Avalon-ST receive path, the incoming TLP contains the ECRC dword and the TD
bit is set if an ECRC exists. On the Avalon-ST transmit path, the TLP from the
application must contain the ECRC dword and have the TD bit set.
If you turn this option On, the RX and TX datapaths are parity protected. This option
is only available for Stratix V GX devices. Parity is even.
Systems which do not support ECRC forwarding can alternatively use parity
protection across the transaction and application layers to complement link CRC
(LCRC) data checking.
On the RX path from the data link layer, parity is generated before checking LCRC
and is propagated to the application and transaction layers. On the TX path, you
must generate parity across the entire width of the TX bus, either 64 or 128 bits,
including unused bytes. Parity is checked after creating the LCRC in the data link
layer.
Indicates the number of messages the application requests. Sets the value of the
multiple message capable field of the message control register, 0x050[31:16]. The
SOPC Builder design flow supports only 1 MSI.
Indicates whether the MSI capability message control register is 64-bit addressing
capable. PCI Express native endpoints always support MSI 64-bit addressing.
0x0001b Range A
0x0010b Range B
0x0011b Ranges A and B
0x0110b Ranges B and C
0x0111b Ranges A, B, and C
0x1110b Ranges B, C and D
0x1111b Ranges A, B, C, and D
MSI Capabilities
Error Reporting
0x050–0x05C
0x800–0x834
Description
December 2010 Altera Corporation
Chapter 3: Parameter Settings
Capabilities Parameters