IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 245

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Chaining DMA Design Example
December 2010 Altera Corporation
Chaining DMA Descriptor Tables
1
Table 15–10
shared memory. It consists of a four-dword descriptor header and a contiguous list of
<n> four-dword descriptors. The endpoint chaining DMA application accesses the
Chaining DMA descriptor table for two reasons:
■
■
Each subsequent descriptor consists of a minimum of four dwords of data and
corresponds to one DMA transfer. (A dword equals 32 bits.)
Note that the chaining DMA descriptor table should not cross a 4 KByte boundary.
Table 15–10. Chaining DMA Descriptor Table
Byte Address Offset to
Base Source
0x0
0x4
0x8
0xC
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
. . .
0x ..0
0x ..4
0x ..8
0x ..C
To iteratively retrieve four-dword descriptors to start a DMA
To send update status to the RP, for example to record the number of descriptors
completed to the descriptor header
describes the Chaining DMA descriptor table which is stored in the BFM
Descriptor Type
Descriptor Header
Descriptor 0
Descriptor 1
Descriptor <n>
Description
Reserved
Reserved
Reserved
EPLAST - when enabled by the EPLAST_ENA bit
in the control register or descriptor, this location
records the number of the last descriptor
completed by the chaining DMA module.
Control fields, DMA length
Endpoint address
RC address upper dword
RC address lower dword
Control fields, DMA length
Endpoint address
RC address upper dword
RC address lower dword
Control fields, DMA length
Endpoint address
RC address upper dword
RC address lower dword
PCI Express Compiler User Guide
15–17