IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 167

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Reset and Clocks
Clocks
Clocks
December 2010 Altera Corporation
Avalon-ST Interface—Hard IP Implementation
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This section describes clocking for the PCI Express IP core. It includes the following
sections:
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When implementing the Arria II GX, Cyclone IV GX, HardCopy IV GX, Stratix IV GX,
or Stratix V GX PHY in a ×1, ×4, or ×8 configuration, the 100 MHz reference clock is
connected directly to the transceiver. core_clk_out is driven by the output of the
transceiver. core_clk_out must be connected back to the pld_clk input clock,
possibly through a clock distribution circuit required by the specific application. The
user application interface is synchronous to the pld_clk input.
npor—The npor reset is used internally for all sticky registers that may not be reset
in L2 low power mode or by the fundamental reset. npor is typically generated by
a logical OR of the power-on-reset generator and the perst# signal as specified in
the PCI Express Card electromechanical Specification.
rstn—The rstn signal is an asynchronous reset of the datapath state machines and
the nonsticky configuration space registers. Whenever the l2_exit, hotrst_exit,
dlup_exit, or other power-on-reset signals are asserted, rstn should be asserted
for one or more cycles. When the perst# signal is asserted, rstn should be asserted
for a longer period of time to ensure that the root complex is stable and ready for
link training.
Avalon-ST Interface—Hard IP Implementation
Avalon-ST Interface—Soft IP Implementation
Clocking for a Generic PIPE PHY and the Simulation Testbench
Avalon-MM Interface–Hard IP and Soft IP Implementations
PCI Express Compiler User Guide
7–7