IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 113

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–8. ECC Error Signals for Hard IP Implementation
Table 5–9. Interrupt Signals for Endpoints
December 2010 Altera Corporation
derr_cor_ext_rcv[1:0]
derr_rpl
derr_cor_ext_rpl
r2c_err0
r2c_err1
Note to
(1) These signals are not available for the hard IP implementation in Arria II GX devices.
(2) The Avalon-ST rx_st_err<n> described in
(3) This signal applies only when ECC is enabled in some hard IP configurations. Refer to
app_msi_req
app_msi_ack
app_msi_tc[2:0]
app_msi_num[4:0]
cfg_msicsr[15:0]
pex_msi_num[4:0]
app_int_sts
app_int_ack
Table
ECC Error Signals
PCI Express Interrupts for Endpoints
Signal
(3)
5–8:
Signal
(3)
Table 5–8
Table 5–9
I/O
(3)
O
O
O
I
I
I
I
I
Application MSI request. Assertion causes an MSI posted write TLP to be generated based
on the MSI configuration register values and the app_msi_tc and app_msi_num input
ports.
Application MSI acknowledge. This signal is sent by the IP core to acknowledge the
application's request for an MSI interrupt.
Application MSI traffic class. This signal indicates the traffic class used to send the MSI
(unlike INTX interrupts, any traffic class can be used to send MSIs).
Application MSI offset number. This signal is used by the application to indicate the offset
between the base message data and the MSI to send.
Configuration MSI control status register. This bus provides MSI software control. Refer to
Table 5–10
Power management MSI number. This signal is used by power management and/or hot
plug to determine the offset between the base message interrupt number and the message
interrupt number to send through MSI.
Controls legacy interrupts. Assertion of app_int_sts causes an Assert_INTA message
TLP to be generated and sent upstream. Deassertion of app_int_sts causes a
Deassert_INTA message TLP to be generated and sent upstream.
This signal is the acknowledge for app_int_sts. This signal is asserted for at least one
cycle either when the Assert_INTA message TLP has been transmitted in response to the
assertion of the app_int_sts signal or when the Deassert_INTA message TLP has been
transmitted in response to the deassertion of the app_int_sts signal. It is included on the
Avalon-ST interface for the hard IP implementation and the ×1 and ×4 soft IP
implementation. Refer to
timing information.
shows the ECC error signals for the hard IP implementation.
describes the IP core’s interrupt signals for endpoints.
Table 5–2 on page 5–7
I/O
O
O
O
O
O
and
Table 5–11
Indicates a correctable error in the RX buffer for the corresponding virtual
channel.
Indicates an uncorrectable error in the retry buffer.
Indicates a correctable error in the retry buffer.
Indicates an uncorrectable ECC error on VC0.
Indicates an uncorrectable ECC error on VC1
Figure 10–5 on page 10–3
for more information.
(Note 1) (Note 2)
indicates an uncorrectable error in the RX buffer.
Description
Table 1–9 on page 1–14
Description
and
Figure 10–6 on page 10–4
PCI Express Compiler User Guide
for more information.
for
5–29