IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 13

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: Datasheet
Features
Table 1–2. PCI Express IP core Features (Part 1 of 2)
December 2010 Altera Corporation
MegaCore License
Root port
Gen1
Gen2
Avalon Memory-Mapped
(Avalon-MM) Interface
64-bit Avalon Streaming
(Avalon-ST) Interface
128-bit Avalon-ST Interface
256-bit Avalon-ST
interface–Stratix V devices only
Descriptor/Data Interface
Legacy Endpoint
Transaction layer packet type
(TLP)
Maximum payload size
Number of virtual channels
Reordering of out–of–order
completions (transparent to the
application layer)
Requests that cross 4 KByte
address boundary (transparent to
the application layer)
(2)
Feature
Different features are available for the soft and hard IP implementations and for the
three possible design flows.
(1)
In Manager Desing
Free
Supported
×1, ×2, ×4, ×8
×1, ×4, ×8
Not supported
Supported
Supported
Supported
Not supported
Supported
All
128 bytes–2
KBytes
(Stratix IV GX and
Stratix V GX,
HardCopy IV GX),
Arria II GZ,
128 bytes–256
bytes (Arria II GX
and)
Cyclone IV GX)
2 (Stratix IV GX,
HardCopy IV GX,)
1 (Arria II GX,
Arria II GZ,
Stratix V GX,
Cyclone IV GX)
Not supported
Not supported
MegaWizard Plug-
Flow
Hard IP Implementation
Table 1–2
Not supported
×1, ×2, ×4
×1
Not supported
Not supported
Not supported
Not supported
1
Free
Supported
Not supported
■
■
■
128–256 bytes
Supported
Supported
SOPC Builder
Memory read
request
Memory write
request
Completion with
or without data
Design Flow
outlines these different features.
In Design Manager
Required
Not supported
×1, ×4, ×8
No
Not supported
Supported
Not supported
Not supported
Supported
Supported
All
128 bytes–2
KBytes
1–2
Not supported
Not supported
MegaWizard Plug-
Flow
Soft IP Implementation
PCI Express Compiler User Guide
Required
Not supported
×1, ×4
No
Supported
Not supported
Not supported
Not supported
Not supported
Not supported
■
■
■
128–256 bytes
1
Supported
Supported
SOPC Builder
Memory read
request
Memory write
request
Completion with
or without data
DesignFlow
1–3