IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 191

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Express Interrupts for Endpoints
MSI Interrupts
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
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This chapter covers interrupts for endpoints and root ports.
The PCI Express Compiler provides support for PCI Express legacy interrupts, MSI
and MSI-X interrupts when configured in endpoint mode. MSI-X interrupts are only
available in the hard IP implementation endpoint variations. The MSI, MSI-X, and
legacy interrupts are mutually exclusive. After power up, the IP core starts in INTX
mode, after which time software decides whether to switch to MSI mode by
programming the msi_enable bit of the MSI message control register (bit[16:] of
0x050) to 1 or to MSI-X mode if you turn on Implement MSI-X on the Capabilities
page using the parameter editor. If you turn on the Implement MSI-X option, you
should implement the MSI-X table structures at the memory space pointed to by the
BARs.
Refer to section 6.1 of
Express interrupt support for endpoints.
MSI interrupts are signaled on the PCI Express link using a single dword memory
write TLPs generated internally by the PCI Express IP core. The app_msi_req input
port controls MSI interrupt generation. When the input port asserts app_msi_req, it
causes a MSI posted write TLP to be generated based on the MSI configuration
register values and the app_msi_tc and app_msi_num input ports.
Figure 10–1
Figure 10–1. MSI Handler Block
illustrates the architecture of the MSI handler block.
PCI Express 2.0 Base Specification
app_msi_req
app_msi_ack
app_msi_tc
app_msi_num
pex_msi_num
app_int_sts
cfg_msicsr[15:0]
MSI Handler
Block
for a general description of PCI
PCI Express Compiler User Guide
10. Interrupts