IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 111

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
December 2010 Altera Corporation
For root ports, srst should be asserted whenever l2_exit, hotrst_exit, dlup_exit,
and power-on-reset signals are asserted. The root port crst signal should be asserted
whenever l2_exit, hotrst_exit and other power-on-reset signals are asserted. When
the perst# signal is asserted, srst and crst should be asserted for a longer period of
time to ensure that the root complex is stable and ready for link training.
The PCI Express IP core soft IP implementation (×8) has two reset inputs, npor and
rstn. The npor reset is used internally for all sticky registers that may not be reset in
L2 low power mode or by the fundamental reset. npor is typically generated by a
logical OR of the power-on-reset generator and the perst# signal as specified in the
PCI Express Card electromechanical Specification.
The rstn signal is an asynchronous reset of the datapath state machines and the
nonsticky configuration space registers. Whenever the l2_exit, hotrst_exit,
dlup_exit, or other power-on-reset signals are asserted, rstn should be asserted for
one or more cycles. When the perst# signal is asserted, rstn should be asserted for a
longer period of time to ensure that the root complex is stable and ready for link
training.
Reset Details for Stratix V Devices
Figure 5–27
Stratix V devices.
Figure 5–27. Reset Domains for Stratix V Devices
pld_clrpmapcship
provides a simplified view of the logic controlled by the reset signals in
perst_n
pld_clrhip_n
<variant>. v or .vhd
<variant> _core.v or .vhd
altpcie_hip_256_pipen1b.v
Datapath State Machines of
Non-Sticky Registers
Configuration Space
Configuration Space
MegaCore Function
SERDES Reset
Sticky Registers
State Machine
PCI Express Compiler User Guide
5–27