IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 92

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–8
Table 5–2. 64-, 128-, or 256-Bit Avalon-ST RX Datapath (Part 2 of 2)
PCI Express Compiler User Guide
Signal
rx_st_bardec<n>
rx_st_be<n>
rx_st_parity
Notes to
(1) In Stratix IV GX devices, <n> is the virtual channel number, which can be 0 or 1.
(2) The RX interface supports a readyLatency of 2 cycles for the hard IP implementation and 3 cycles for the soft IP implementation.
Figure
5–2:
To facilitate the interface to 64-bit memories, the IP core always aligns data to the
qword or 64 bits; consequently, if the header presents an address that is not qword
aligned, the IP core, shifts the data within the qword to achieve the correct alignment.
Figure 5–5
The byte enables only qualify data that is being written. This means that the byte
enables are undefined for 0x0–0x3. This example corresponds to
page
Qword alignment applies to all types of request TLPs with data, including memory
5–10. Qword alignment is a feature of the IP core that cannot be turned off.
Width Dir
8
8
16, 31
8
16, 31
shows how an address that is not qword aligned, 0x4, is stored in memory.
O
O
o
component
specific
component
specific
component
specific
Avalon-ST
Type
Description
The decoded BAR bits for the TLP. They correspond to the
transaction layer's rx_desc[135:128]. Valid for MRd, MWr,
IOWR, and IORD TLPs; ignored for the CPL or message TLPs.
They are valid on the 2nd cycle of rx_st_data<n> for a 64-bit
datapath. For a 128-bit datapath rx_st_bardec<n> is valid on
the first cycle.
of this signal for 64- and 128-bit data, respectively.
These are the byte enables corresponding to the transaction
layer's rx_be. The byte enable signals only apply to PCI
Express TLP payload fields. When using 64-bit Avalon-ST bus,
the width of rx_st_be is 8. When using 128-bit Avalon-ST bus,
the width of rx_st_be is 16. When using a 256-bit Avalon-ST
bus, the width or rx_st_be is 31 bits. This signal is optional.
You can derive the same information decoding the FBE and LBE
fields in the TLP header. The correspondence between byte
enables and data is as follows when the data is aligned:
rx_st_data[63:56] = rx_st_be[7]
rx_st_data[55:48] = rx_st_be[6]
rx_st_data[47:40] = rx_st_be[5]
rx_st_data[39:32] = rx_st_be[4]
rx_st_data[31:24] = rx_st_be[3]
rx_st_data[23:16] = rx_st_be[2]
rx_st_data[15:8] = rx_st_be[1]
rx_st_data[7:0]
Generates even parity on the entire TLP when parity is enabled.
Available for Stratix V devices only.
Figure 5–9
= rx_st_be[0]
and
Figure 5–10
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Figure 5–6 on
illustrate the timing
Avalon-ST Interface