IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 130

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–46
Table 5–23. Completion Signals for the Avalon-ST Interface (Part 2 of 2)
Avalon-MM Application Interface
PCI Express Compiler User Guide
cpl_err[6:0]
(continued)
err_desc_func0
[127:0]
cpl_pending
Signal
You can choose either the soft or hard IP implementation of PCI Express IP core when
using the SOPC Builder design flow. The hard IP implementation is available as a full-
featured endpoint or a completer-only single dword endpoint.
I/O
I
I
■
Refer to the
information about LMI signalling.
For the ×8 soft IP, only bits [3:1] of cpl_err are available. For the ×1, ×4 soft IP
implementation and all widths of the hard IP implementation, all bits are
available.
TLP Header corresponding to a cpl_err. Logged by the IP core when
cpl_err[6] is asserted. This signal is only available for the ×1 and ×4 soft IP
implementation. In the hard IP implementation, this information can be written to
the AER header log register through the LMI interface. If AER is not implemented
in your variation this bus should be tied to all 0’s.
Completion pending. The application layer must assert this signal when a master
block is waiting for completion, for example, when a transaction is pending. If
this signal is asserted and low power mode is requested, the IP core waits for the
deassertion of this signal before transitioning into low-power state.
cpl_err[6]: Log header. When asserted, logs err_desc_func0 header.
Used in both the soft IP and hard IP implementation of the IP core that use the
Avalon-ST interface.
When asserted, the TLP header is logged in the AER header log register if it is
the first error detected. When used, this signal should be asserted at the same
time as the corresponding cpl_err error bit (2, 3, 4, or 5).
In the soft IP implementation, the application presents the TLP header to the
IP core on the err_desc_func0 bus. In the hard IP implementation, the
application presents the header to the IP core by writing the following values
to 4 registers via LMI before asserting cpl_err[6]:
■
■
■
■
lmi_addr: 12'h81C, lmi_din: err_desc_func0[127:96]
lmi_addr: 12'h820, lmi_din: err_desc_func0[95:64]
lmi_addr: 12'h824, lmi_din: err_desc_func0[63:32]
lmi_addr: 12'h828, lmi_din: err_desc_func0[31:0]
“LMI Signals—Hard IP Implementation” on page 5–40
Description
December 2010 Altera Corporation
Avalon-MM Application Interface
Chapter 5: IP Core Interfaces
for more