IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 94

IP CORE Renewal Of IP-PCIE/1

IPR-PCIE/1

Manufacturer Part Number
IPR-PCIE/1
Description
IP CORE Renewal Of IP-PCIE/1
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-PCIE/1

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x1 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
5–10
Figure 5–6. 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-DWord Header TLPs with Non-QWord Aligned Address
Figure 5–7. 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-DWord Header TLPs with QWord Aligned Address
Note to
(1) rx_st_be[7:4] corresponds to rx_st_data[63:32]. rx_st_be[3:0] corresponds to rx_st_data[31:0]
Figure 5–8. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-DWord Header TLPs with QWord Aligned Addresses
PCI Express Compiler User Guide
(Note 1)
rx_st_data[63:32]
rx_st_data[31:0]
Figure
rx_st_be[7:4]
rx_st_be[3:0]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
5–7:
rx_st_eop
rx_st_sop
1
rx_st_data[63:32]
clk
rx_st_data[31:0]
rx_st_be[7:4]
rx_st_be[3:0]
clk
rx_st_sop
rx_st_eop
Note that the Avalon-ST protocol, as defined in
endian, while the PCI Express IP core packs symbols into words in little endian
format. Consequently, you cannot use the standard data format adapters available in
SOPC Builder with PCI Express IP cores that use the Avalon-ST interface.
Figure 5–7
three dword header with qword aligned addresses. Note that the byte enables
indicate the first byte of data is not valid and the last dword of data has a single valid
byte.
Figure 5–8
for a four dword with qword aligned addresses with a 64-bit bus.
clk
Header1
Header0
shows the mapping of Avalon-ST RX packets to PCI Express TLPs for TLPs
illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a
Header 1
Header 0
header1
header0
Header2
Header2
header3
header2
Data0
F
Data1
Data0
F
E
Avalon Interface
Data3
Data2
F
1
data1
data0
December 2010 Altera Corporation
Data2
Data1
F
F
F
F
Specifications, is big
Chapter 5: IP Core Interfaces
Avalon-ST Interface

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