IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 353

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Revision History
December 2010 Altera Corporation
December
2010
Date
Version
10.1
This chapter provides additional information about the document and Altera.
The table below displays the revision history for the chapters in this User Guide.
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Added support for the following new features in Stratix V devices:
Added support for soft IP implementation of PCI Express IP core in Cyclone IV GX with
Avalon-ST interface
Added support for Arria II GZ with Avalon-ST interface
Revised description of reset logic to reflect changes in the implementation. Added new free
running fixedclk, busy_reconfig_altgxb_reconfig, and
reset_reconfig_altgxb_reconfig signals to hard IP implementation in Arria II GX,
Arria II GZ, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX devices.
Added CBB module to testbench to provide push button access for CBB testing
The ECC error signals, derr_*, r2c_err0, and rx_st_err<0> are not available in the hard IP
implementation of the PCI Express IP core for Arria II GX devices.
Corrected Type field of the Configuration Write header in
should be 5’b00101, not 5’b00010.
Improved description of AVL_IRQ_INPUT_VECTOR in
Corrected size of tx_cred signal for soft IP implementation in
36 bits, not 22 bits.
Clarified behavior of the rx_st_valid signal in the hard IP implementation of Arria II GX,
Cyclone IV GX, HardCopy, and Stratix IV GX devices in
Added fact that tx_st_err is not available for packets that are 1 or 2 cycles long in
Table 5–4 on page
Updated
64-bit and 128-bit mode. Also added discussion of .sdc timing constraints for the
tl_cfg_ctl_wr and tl_cfg_sts_wr . .
Corrected bit definitions for Max Payload and Max Read Request Size in
page
Corrected description of dynamic reconfiguration in
Cancellation. Link is brought down by asserting pcie_reconfig_rstn, not npor.
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256-bit interface
Simulation support
5–36.
Figure 5–30 on page 5–33
5–13.
and
Changes Made
Figure 5–32 on page 5–33
Additional Information
Chapter 13, Reconfiguration and Offset
Table 6–13 on page
Figure 5–2 on page
Table A–13 on page
Figure 5–3 on page
PCI Express Compiler User Guide
to include pld_clk in
Table 5–15 on
6–7.
5–3.
A–4. The value
5–4. It is
SPR