IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 330

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–24
Figure B–21. TX Multiple Wait States that Throttle Data Transmission Waveform
Figure B–22. TX Error Assertion Waveform
PCI Express Compiler User Guide
Descriptor
Descriptor
Signals
Signals
Data
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_desc[127:0]
tx_data[63:32]
tx_data[63:32]
tx_data[31:0]
In clock cycles 5, 7, 9, and 11, the IP core inserts wait states to throttle the flow of
transmission.
Error Asserted and Transmission Is Nullified
In this example, the application transmits a 64-bit memory write transaction of 14
DWORDS. Address bit 2 is set to 0. Refer to
In clock cycle 12, tx_err is asserted which nullifies transmission of the transaction
layer packet on the link. Nullified packets have the LCRC inverted from the
calculated value and use the end bad packet (EDB) control character instead of the
normal END control character.
tx_ack
tx_req
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
tx_ws
tx_err
tx_dfr
tx_dv
clk
clk
1
1
2
2
MEMWR64
MEMWR64
3
3
DW 0
DW 1
DW 1
DW 0
4
4
DW 2
DW 3
5
5
DW 3
DW 2
DW 5
DW 4
6
6
DW 5
DW 4
7
7
DW 7
DW 6
Figure
DW 7
DW 6
8
8
DW 9
DW 8
B–22.
9
9
DW B
DW A
DW 9
DW 8
10
10
DW D
DW C
December 2010 Altera Corporation
11
11
DW E
DW F
DW 11
DW 10
12
12
Descriptor/Data Interface
13
13
14
Chapter :
14