IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 316

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–10
Figure B–8. RX Transaction with a Data Payload Waveform
PCI Express Compiler User Guide
Descriptor
Signals
Data
Signals
rx_desc[135:128]
rx_desc[127:64]
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
Normally, rx_dfr is asserted on the same or following clock cycle as rx_req; however,
in this case the signal is already asserted until clock cycle 7 to signal the end of
transmission of the first transaction. It is immediately reasserted on clock cycle eight
to request a data phase for the second transaction.
rx_be[7:0]
Transaction with Data Payload and Wait States
The application layer can assert rx_ws without restrictions. In
receives a completion transaction of four DWORDS. Bit 2 of rx_data[63:0] is set to 1.
Both the application layer and the IP core insert wait states. Normally rx_data[63:0]
would contain data in clock cycle 4, but the IP core has inserted a wait state by
deasserting rx_dv.
In clock cycle 11, data transmission does not resume until both of the following
conditions are met:
■
rx_mask
rx_abort
rx_retry
rx_ack
rx_req
The IP core asserts rx_dv at clock cycle 10, thereby ending a IP core-induced wait
state.
rx_ws
rx_dfr
rx_dv
clk
1
2
CPLD 8 DW
3
valid
valid
4
DW 1
DW 0
5
DW 3
DW 2
6
DW 5
DW 4
0xFF
7
DW 7
DW 6
8
December 2010 Altera Corporation
9
MEMWR/AD 3 DW
Figure
DW 0
valid
valid
0x0F
Descriptor/Data Interface
B–9, the IP core
11
DW 2
DW 1
0xFF
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