IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 201

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Table 12–1. Error Classification
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
Correctable
Uncorrectable, non-fatal
Uncorrectable, fatal
Type
Each PCI Express compliant device must implement a basic level of error
management and can optionally implement advanced error management. The Altera
PCI Express IP core implements both basic and advanced error reporting. Given its
position and role within the fabric, error handling for a root port is more complex than
that of an endpoint.
The PCI Express specifications defines three types of errors, outlined in
The following sections describe the errors detected by the three layers of the PCI
Express protocol and describes error logging. It includes the following sections:
■
■
■
■
Physical Layer Errors
Data Link Layer Errors
Transaction Layer Errors
Error Reporting and Data Poisoning
Hardware
Device software
System software
Responsible
Agent
While correctable errors may affect system performance, data integrity is
maintained.
Uncorrectable, non-fatal errors are defined as errors in which data is lost,
but system integrity is maintained. For example, the fabric may lose a
particular TLP, but it still works without problems.
Errors generated by a loss of data and system failure are considered
uncorrectable and fatal. Software must determine how to handle such
errors: whether to reset the link or implement other means to minimize
the problem.
Description
12. Error Handling
PCI Express Compiler User Guide
Table
12–1.