IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 246

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–18
Table 15–11. Chaining DMA Descriptor Format Map
Table 15–12. Chaining DMA Descriptor Format Map (Control Fields)
Table 15–13. Chaining DMA Descriptor Fields
Test Driver Module
PCI Express Compiler User Guide
3122
2118
Endpoint Address
RC Address
Upper DWORD
RC Address
Lower DWORD
DMA Length
EPLAST_ENA
MSI_ENA
Descriptor Field
Reserved
Endpoint
Access
Table 15–11
Each descriptor provides the hardware information on one DMA transfer.
describes each descriptor field.
The BFM driver module generated by the MegaWizard interface during the generate
step is configured to test the chaining DMA example endpoint design. The BFM
driver module configures the endpoint configuration space registers and then tests
the example endpoint chaining DMA channel.
For an endpoint VHDL version of this file, see:
<variation_name>_examples/chaining_dma/testbench/
altpcietb_bfm_driver_chaining.vhd
For an endpoint Verilog HDL file, see:
<variation_name>_examples/chaining_dma/testbench/
altpcietb_bfm_driver_chaining.v
R
R
R
R
R
R
RC Access
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
shows the layout of the descriptor fields following the descriptor header.
21 16
Control Fields (refer to
A 32-bit field that specifies the base address of the memory transfer on the
endpoint site.
Specifies the upper base address of the memory transfer on the RC site.
Specifies the lower base address of the memory transfer on the RC site.
Specifies the number of DMA DWORDs to transfer.
This bit is OR’d with the EPLAST_ENA bit of the control register. When
EPLAST_ENA is set, the endpoint DMA module updates the EPLAST field of
the descriptor table with the number of the last completed descriptor, in the
form <0 – n>. (Refer to
This bit is OR’d with the MSI bit of the descriptor header. When this bit is set
the endpoint DMA module sends an interrupt when the descriptor is
completed.
RC Address Upper DWORD
RC Address Lower DWORD
Endpoint Address
Table
15–12)
Table
15–10.)
150
Description
Chapter 15: Testbench and Design Example
EPLAST_ENA
17
December 2010 Altera Corporation
DMA Length
Test Driver Module
Table 15–13
MSI
16