IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 124

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–40
Table 5–17. Configuration Space Signals (Part 2 of 2)(Soft IP Implementation)
PCI Express Compiler User Guide
cfg_devcsr[31:0]
cfg_linkcsr[31:0]
LMI Signals—Hard IP Implementation
Signal
LMI writes log error descriptor information in the AER header log registers. These
writes record completion errors as described in
ST Interface” on page
Altera does not recommend using the LMI bus to access other configuration space
registers for the following reasons:
■
■
Figure 5–36
Figure 5–36. Local Management Interface
The LMI interface is synchronized to pld_clk and runs at frequencies up to 250 MHz.
The LMI address is the same as the PCIe configuration space address. The read and
write data are always 32 bits. The LMI interface provides the same access to
configuration space registers as configuration TLP requests. Register bits have the
same attributes, (read only, read/write, and so on) for accesses from the LMI interface
and from configuration TLP requests.
LMI write—An LMI write updates the internally captured bus and device
numbers incorrectly; however, configuration writes received from the PCIe link
provide the correct bus and device numbers.
LMI read—For other configuration space registers, an LMI request can fail to be
acknowledged if it occurs at the same time that a configuration request is
processed from the RX Buffer. Simultaneous requests may lead to collisions that
corrupt the data stored in the configuration space registers.
I/O
O
O
Configuration device control status register. Refer to the
for details.
Configuration link control status register. Refer to the
details.
illustrates the LMI interface.
lmi_dout
lmi_ack
lmi_rden
lmi_wren
lmi_addr
lmi_din
12
5–45.
32
32
pld_clk
LMI
Description
“Completion Signals for the Avalon-
Configuration Space
128 32-bit registers
MegaCore Function
PCI Express Base Specification
(4 KBytes)
PCI Express
PCI Express Base Specification
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface
for