IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 71

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
Physical Layer
Physical Layer
December 2010 Altera Corporation
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1. Initialize FC data link layer packet
2. ACK/NAK data link layer packet (high priority)
3. Update FC data link layer packet (high priority)
4. PM data link layer packet
5. Retry buffer transaction layer packet
6. Transaction layer packet
7. Update FC data link layer packet (low priority)
8. ACK/NAK FC data link layer packet (low priority)
The physical layer is the lowest level of the IP core. It is the layer closest to the link. It
encodes and transmits packets across a link and accepts and decodes received
packets. The physical layer connects to the link through a high-speed SERDES
interface running at 2.5 Gbps for Gen1 implementations and at 2.5 or 5.0 Gbps for
Gen2 implementations. Only the hard IP implementation supports the Gen2 rate.
The physical layer is responsible for the following actions:
Data Link Control and Management State Machine—This state machine is
synchronized with the physical layer’s LTSSM state machine and is also connected
to the configuration space registers. It initializes the link and virtual channel flow
control credits and reports status to the configuration space. (Virtual channel 0 is
initialized by default, as is a second virtual channel if it has been physically
enabled and the software permits it.)
Power Management—This function handles the handshake to enter low power
mode. Such a transition is based on register values in the configuration space and
received PM DLLPs.
Data Link Layer Packet Generator and Checker—This block is associated with the
data link layer packet’s 16-bit CRC and maintains the integrity of transmitted
packets.
Transaction Layer Packet Generator—This block generates transmit packets,
generating a sequence number and a 32-bit CRC. The packets are also sent to the
retry buffer for internal storage. In retry mode, the transaction layer packet
generator receives the packets from the retry buffer and generates the CRC for the
transmit packet.
Retry Buffer—The retry buffer stores transaction layer packets and retransmits all
unacknowledged packets in the case of NAK DLLP reception. For ACK DLLP
reception, the retry buffer discards all acknowledged packets.
ACK/NAK Packets—The ACK/NAK block handles ACK/NAK data link layer
packets and generates the sequence number of transmitted packets.
Transaction Layer Packet Checker—This block checks the integrity of the received
transaction layer packet and generates a request for transmission of an ACK/NAK
data link layer packet.
TX Arbitration—This block arbitrates transactions, basing priority on the
following order:
PCI Express Compiler User Guide
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