IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 155

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Content
Table 6–19. PCI Express to Avalon-MM Interrupt Status Register
Table 6–20. PCI Express to Avalon-MM Interrupt Enable Register
Table 6–21. Avalon-MM-to-PCI Express Mailbox Registers, Read/Write (Part 1 of 2)
December 2010 Altera Corporation
[15:0]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
[23]
[31:24]
0x3A00
0x3A04
Address
[23:16]
[31:24]
[15:0]
Bits
Bits
Avalon-MM Mailbox Registers
Reserved
P2A_MAILBOX_INT0
P2A_MAILBOX_INT1
P2A_MAILBOX_INT2
P2A_MAILBOX_INT3
P2A_MAILBOX_INT4
P2A_MAILBOX_INT5
P2A_MAILBOX_INT6
P2A_MAILBOX_INT7
Reserved
Reserved
P2A_MB_IRQ
Reserved
A2P_MAILBOX0
A2P _MAILBOX1
Name
The interrupt status register
cause an Avalon-MM interrupt to be asserted.
An Avalon-MM interrupt can be asserted for any of the conditions noted in the
Avalon-MM interrupt status register by setting the corresponding bits in the interrupt
enable register
PCI Express interrupts can also be enabled for all of the error conditions described.
However, it is likely that only one of the Avalon-MM or PCI Express interrupts can be
enabled for any given bit. There is typically a single process in either the PCI Express
or Avalon-MM domain that is responsible for handling the condition reported by the
interrupt.
A processor local to the system interconnect fabric typically requires write access to a
set of Avalon-MM-to-PCI Express mailbox registers and read-only access to a set of
PCI Express-to-Avalon-MM mailbox registers. Eight mailbox registers are available.
The Avalon-MM-to-PCI Express mailbox registers are writable at the addresses shown
in
corresponding bit in the PCI Express interrupt status register is set to 1.
Name
Name
Table
6–21. When the Avalon-MM processor writes to one of these registers the
Access
(Table
RW
RW
Access
Access
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW
—
—
—
—
6–20).
Avalon-MM-to-PCI Express mailbox 0
Avalon-MM-to-PCI Express mailbox 1
1 when the P2A_MAILBOX0 is written
1 when the P2A_MAILBOX1 is written
1 when the P2A_MAILBOX2 is written
1 when the P2A_MAILBOX3 is written
1 when the P2A_MAILBOX4 is written
1 when the P2A_MAILBOX5 is written
1 when the P2A_MAILBOX6 is written
1 when the P2A_MAILBOX7 is written
(Table
Enables assertion of Avalon-MM interrupt CraIrq_o signal when
the specified mailbox is written by the root complex.
6–19) records the status of all conditions that can
Description
Description
Description
—
—
—
—
Address Range: 0x3A00-0x3A1F
PCI Express Compiler User Guide
Address: 0x3070
Address: 0x3060
6–11