IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 67

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
Transaction Layer
Figure 4–6. PCI Express IP core with Avalon-MM Interface
Transaction Layer
December 2010 Altera Corporation
(Control Register
Avalon-MM Interface
Avalon-MM
Master Port
Avalon-MM
Avalon-MM
Slave Port
Slave Port
Access)
1
To Application Layer
The PCI Express endpoint which results from the SOPC Builder flow comprises a PCI
Express Avalon-MM bridge that interfaces to hard IP implementation with a soft IP
implementation of the transaction layer optimized for the Avalon-MM protocol.
The PCI Express Avalon-MM bridge provides an interface between the PCI Express
transaction layer and other SOPC Builder components across the system interconnect
fabric.
The transaction layer sits between the application layer and the data link layer. It
generates and receives transaction layer packets.
layer of a component with two initialized virtual channels (VCs). The transaction
layer contains three general subblocks: the transmit datapath, the configuration space,
and the receive datapath, which are shown with vertical braces in
page
You can parameterize the Stratix IV GX IP core to include one or two virtual channels.
The Arria II GX, Cyclone IV GX, and Stratix V GX implementations include a single
virtual channel.
Tracing a transaction through the receive datapath includes the following steps:
1. The transaction layer receives a TLP from the data link layer.
2. The configuration space determines whether the transaction layer packet is well
3. Within each virtual channel, transaction layer packets are stored in a specific part
PCI Express IP Core
SOPC Builder
component controls
the upstream PCI
Express devices.
SOPC Builder
component controls
access to internal
control and status
registers.
Root port controls the
downstream SOPC
Builder component.
Avalon-MM Interface
formed and directs the packet to the appropriate virtual channel based on traffic
class (TC)/virtual channel (VC) mapping.
of the receive buffer depending on the type of transaction (posted, non-posted,
and completion).
4–10.
PCI Express
With information sent
by the application
layer, the transaction
layer generates a TLP,
which includes a
header and, optionally,
a data payload.
The transaction layer
disassembles the
transaction and
transfers data to the
application layer in a
form that it recognizes.
Transaction Layer
The data link layer
ensures packet
integrity, and adds a
sequence number and
link cyclic redundancy
code (LCRC) check to
the packet.
The data link layer
verifies the packet's
sequence number and
checks for errors.
Data Link Layer
Figure 4–7
The physical layer
encodes the packet
and transmits it to the
receiving device on the
other side of the link.
The physical layer
decodes the packet
and transfers it to the
data link layer.
Physical Layer
illustrates the transaction
PCI Express Compiler User Guide
Figure 4–7 on
To Link
Tx
Rx
4–9