IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 89

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Figure 5–4. Signals in the Hard IP Implementation with Avalon-ST Interface for Stratix V Devices
December 2010 Altera Corporation
Reset &
Training
Link
<variant>
Tx Port
<variant>_plus
Reconfiguration
(optional)
Completion
Interface
ECC Error
Component
Interrupts
(Root Port)
Block
Clocks
Component
Avalon-ST
Avalon-ST
Specific
Specific
perst_n
dl_ltssm[4:0]
pld_clk_ready
pld_clk_in_use
reset_status
l2_exit
hotrst_exit
dlup_exit
pld_clrhip_n
pld_clrpmapcship
rc_pll_locked
avs_pcie_reconfig_address[7:0]
avs_pcie_reconfig_byteenable[1:0]
avs_pcie_reconfig_chipselect
avs_pcie_reconfig_write
avs_pcie_reconfig_writedata[15:0]
avs_pcie_reconfig_waitrequest
avs_pcie_reconfig_read
avs_pcie_reconfig_readdata[15:0]
avs_pcie_reconfig_readdatavalid
avs_pcie_reconfig_clk
avs_pcie_reconfig_rstn
tx_st_ready
tx_st_valid
tx_st_data[63:0], [127:0], [255:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_err
tx_fifo_full
tx_fifo_empty
tx_fifo_rdptr[3:0]
tx_fifo_wrptr[3:0]
tx_cred_datafccp[11:0]
tx_cred_datafcnp[11:0]
tx_cred_datafcp[11:0]
tx_cred_fchipons[5:0]
tx_cred_fcinfinite[5:0]
tx_cred_hdrfccp[7:0]
tx_cred_hdrfcnp[7:0]
tx_cred_hdrfcp[7:0]
tx_st_parity[7:0], [15:0], [31:0]
refclk
pld_clk
core_clk_out
derr_cor_ext_rcv[1:0]
derr_rpl
derr_cor_ext_rpl
r2c_err0
r2c_err1
rx_st_ready
rx_st_valid
rx_st_data[63:0], [127:0], [255:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_err
rx_st_mask
rx_st_bardec[7:0]
rx_st_be[7:0], [15:0], [31:0]
rx_st_parity[7:0], [15:0], [31:0]
aer_msi_num[4:0]
pex_msi_num[4:0]
int_status[4:0]
serr_out
cpl_err[6:0]
cpl_pending
Signals in the PCI Express Hard IP Core Stratix V
(1)
(2)
powerdown0_ext[1:0]
reconfig_fromgxb[:0]
reconfig_togxb[:0]
rxstatus0_ext[2:0]
app_msi_num[4:0]
gxb_powerdown
pex_msi_num[4:0]
rx_st_fifo_empty
txdata0_ext[7:0]
rxdata0_ext[7:0]
tl_cfg_sts[52:0]
txdetectrx0_ext
tx_pipedeemph
phystatus0_ext
tl_cfg_add[3:0]
txelecidle0_ext
rxelecidle0_ext
tl_cfg_ctl[31:0]
hpg_ctrler[4:0]
rxpolarity0_ext
lmi_addr[11:0]
app_msi_tc[2:0]
lmi_dout[31:0]
tx_pipemargin
test_out[63:0]
tl_cfg_sts_wr
rx_st_fifo_full
txcompl0_ext
lmi_din[31:0]
lane_act[3:0]
rxdatak0_ext
tl_cfg_ctl_wr
txdatak0_ext
reconfig_clk
test_in[39:0]
rxvalid0_ext
app_msi_ack
pm_auxpwr
app_msi_req
cal_blk_clk
pipe_mode
pme_to_cr
pme_to_sr
clk250_out
clk500_out
pipe_txclk
pm_event
pipe_rstn
lmi_wren
lmi_rden
pm_data
rate_ext
lmi_ack
tx_out0
tx_out1
tx_out2
tx_out3
tx_out4
tx_out5
tx_out6
tx_out7
pclk_in
rx_in0
rx_in1
rx_in2
rx_in3
rx_in4
rx_in5
rx_in6
rx_in7
PCI Express Compiler User Guide
<variant>_plus.v or .vhd)
8-bit
PIPE
Simulation
Test
Interface
Config
Interrupt
(Endpoint)
Serial
Clocks -
Power
Mnmt
internal
LMI
IF to
PIPE
Only
PHY
These signals are
for
Transceiver
internal for
Control
Simulation
Interface
PIPE
Only
5–5