IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 69

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
Transaction Layer
December 2010 Altera Corporation
Transmit Virtual Channel Arbitration
Configuration Space
f
Tracing a transaction through the transmit datapath involves the following steps:
1. The IP core informs the application layer that sufficient flow control credits exist
2. The application layer requests a transaction layer packet transmission. The
3. The IP core verifies that sufficient flow control credits exist, and acknowledges or
4. The transaction layer packet is forwarded by the application layer. The transaction
For Stratix IV GX devices, the PCI Express IP core allows you to specify a high and
low priority virtual channel as specified in Chapter 6 of the
Specification 1.0a, 1.1 or
accessible from the Parameter Settings tab, to specify the number of virtual channels.
Refer to
The configuration space implements the following configuration registers and
associated functions:
■
■
■
■
■
■
■
The configuration space also generates all messages (PME#, INT, error, slot power
limit), MSI requests, and completion packets from configuration requests that flow in
the direction of the root complex, except slot power limit messages, which are
generated by a downstream port in the direction of the PCI Express link. All such
transactions are dependent upon the content of the PCI Express configuration space
as described in the
Refer To
Express Base Specification 1.0a, 1.1 or 2.0
for a particular type of transaction. The IP core uses tx_cred[21:0] for the soft IP
implementation and tx_cred[35:0] for the hard IP implementation. The
application layer may choose to ignore this information.
application layer must provide the PCI Express transaction and must be prepared
to provide the entire data payload in consecutive cycles.
postpones the request.
layer arbitrates among virtual channels, and then forwards the priority transaction
layer packet to the data link layer.
Header Type 0 Configuration Space for Endpoints
Header Type 1 Configuration Space for Root Ports
PCI Power Management Capability Structure
Message Signaled Interrupt (MSI) Capability Structure
Message Signaled Interrupt–X (MSI–X) Capability Structure
PCI Express Capability Structure
Virtual Channel Capabilities
“Buffer Setup Parameters” on page
“Configuration Space Register Content” on page 6–1
PCI Express Base Specification Revision 1.0a, 1.1, 2.0, or
2.0. You can use the settings on the Buffer Setup page,
for the complete content of these registers.
3–10.
PCI Express Base
PCI Express Compiler User Guide
or Chapter 7 in the
2.1.
PCI
4–11