IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 237

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Chaining DMA Design Example
Figure 15–4. Top-Level Chaining DMA Example for Simulation—Hard IP Implementation with PCIE Reconfig Block
December 2010 Altera Corporation
DMA Write
Chaining DMA
Endpoint Memory
Control Register
Avalon-MM
interfaces
RC Slave
DMA Read
■
■
The example endpoint design application layer accomplishes the following objectives:
■
■
■
■
You can use the example endpoint design in the testbench simulation and compile a
complete design for an Altera device. All of the modules necessary to implement the
design example with the variation file are contained in one of the following files,
based on the language you use:
<variation name>_examples/chaining_dma/example_chaining.vhd
or
<variation name>_examples/chaining_dma/example_chaining.v
These files are created in the project directory when files are generated.
The design example exercises the optional ECRC module when targeting the hard
IP implementation using a variation with both Implement advanced error
reporting and ECRC forwarding set to On in the
page
The design example exercises the optional PCI Express reconfiguration block
when targeting the hard IP implementation created using the MegaWizard Plug-In
manager if you selected PCIe Reconfig on the System Settings page.
illustrates this test environment.
Shows you how to interface to the PCI Express IP core in Avalon-ST mode, or in
descriptor/data mode through the ICM. Refer to
Compile Module for Descriptor/Data
Provides a chaining DMA channel that initiates memory read and write
transactions on the PCI Express link.
If the ECRC forwarding functionality is enabled, provides a CRC Compiler IP core
to check the ECRC dword from the Avalon-ST RX path and to generate the ECRC
for the Avalon-ST TX path.
If the PCI Express reconfiguration block functionality is enabled, provides a test
that increments the Vendor ID register to demonstrate this functionality.
3–7.
PCIE Reconfig
CBB Test
Driver
Driver
to test_in[5,32] altpcierd_compliance_test.v
Configuration
Avalon-ST
Avalon-MM
<variant>_plus
Implementation)
Calibration
MegaCore
Function
Variation
Express
(Hard IP
Reset
PCI
Examples.
PCI Express
Appendix C, Incremental
“Capabilities Parameters” on
Descriptor
Root Complex
Read
Table
PCI Express Compiler User Guide
Memory
Root Port
Data
CPU
Descriptor
Write
Table
Figure 15–4
15–9