IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 45

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
System Settings
Table 3–1. System Settings Parameters (Part 3 of 4)
December 2010 Altera Corporation
Xcvr ref_clk
PHY pclk
Application Interface
Port type
PCI Express version
Application clock
Max rate
Parameter
100 MHz, 125 MHz
64-bit Avalon-ST,
128-bit Avalon-ST,
Descriptor/Data,
Avalon-MM
Native Endpoint
Legacy Endpoint
Root Port
1.0A, 1.1, 2.0, 2.1
62.5 MHz
125 MHz
250 MHz
Gen 1 (2.5 Gbps)
Gen 2 (5.0 Gbps)
Value
For Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX, you
can select either a 100 MHz or 125 MHz reference clock for Gen1
operation; Gen2 requires a 100 MHz clock. The Arria GX and
Stratix II GX devices require a 100 MHz clock. If you use a PIPE
interface (and the PHY type is not Arria GX, Arria II GX, Cyclone IV GX,
HardCopy IV GX, Stratix II GX, or Stratix IV GX) the refclk is not
required.
For Custom and TI X101100 PHYs, the PHY pclk frequency is 125 MHz.
For the NXP PX1011A PHY, the pclk value is 250 MHz.
Specifies the interface between the PCI Express transaction layer and the
application layer. When using the MegaWizard Plug-In Manager flow,
this parameter can be set to Avalon-ST or Descriptor/Data. Altera
recommends the Avalon-ST option for all new designs. When using the
SOPC Builder design flow this parameter is read-only and set to
Avalon-MM. 128-bit Avalon-ST is only available when using the hard IP
implementation.
Specifies the port type. Altera recommends Native Endpoint for all new
endpoint designs. Select Legacy Endpoint only when you require I/O
transaction support for compatibility. The SOPC Builder design flow only
supports Native Endpoint and the Avalon-MM interface to the user
application. The Root Port option is available in the hard IP
implementations.
The endpoint stores parameters in the Type 0 configuration space which
is outlined in
the Type 1 configuration space which is outlined in
page
Selects the PCI Express specification with which the variation is
compatible. Depending on the device that you select, the PCI Express
hard IP implementation supports PCI Express versions 1.1, 2.0, and
2.1. The PCI Express soft IP implementation supports PCI Express
versions 1.0a and 1.1
Specifies the frequency at which the application interface clock operates.
This frequency can only be set to 62.5 MHz or 125 MHz for Gen1 ×1
variations. For all other variations this field displays the frequency of
operation which is controlled by the number of lanes, application
interface width and Max rate setting. Refer to
a list of the supported combinations.
Specifies the maximum data rate at which the link can operate. The Gen2
rate is only supported in the hard IP implementations. Refer to
for a complete list of Gen1 and Gen2 support in the hard IP
implementation.
6–3.
Table 6–2 on page
Description
6–2. The root port stores parameters in
PCI Express Compiler User Guide
Table 4–1 on page 4–4
Table 6–3 on
Table 3–1
for
3–3