IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 158

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–14
Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description
PCI Express Compiler User Guide
Byte Address
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x050
0x054
0x058
0x05C
0x68
0x6C
0x70
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
Table 6-7.
Table 6-6.
PCI Express Capability Structure Version 1.0a and 1.1 (Note 1), Rev2 Spec: PCI Express Capabilities Register
Table 6-5.
Table
Config Reg Offset 31:24 23:16 15:8 7:0
Base Address 1
Secondary Latency Timer Subordinate Bus
Number Secondary Bus Number Primary Bus
Number
Secondary Status I/O Limit I/O Base
Memory Limit Memory Base
Prefetchable Memory Limit Prefetchable Memory
Base
Prefetchable Base Upper 32 Bits
Prefetchable Limit Upper 32 Bits
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
Reserved Capabilities PTR
Expansion ROM Base Address
Bridge Control Interrupt Pin Interrupt Line
Message Control Next Cap Ptr Capability ID
Message Address
Message Upper Address
Reserved Message Data
Message Control Next Cap Ptr Capability ID
MSI-X Table Offset BIR
Pending Bit Array (PBA) Offset BIR
Capabilities Register Next Cap PTR Cap ID
Data PM Control/Status Bridge Extensions Power
Management Status & Control
PCI Express Capabilities Register Next Cap PTR
Capability ID
Device capabilities
Device Status Device Control
Link capabilities
Link Status Link Control
Slot capabilities
Slot Status Slot Control
Reserved Root Control
Root Status
Power Management Capability Structure, Rev2 Spec: Power Management Capability Structure
6-4.MSI Capability Structure, Rev2 Spec: MSI and MSI-X Capability Structures
MSI-X Capability Structure, Rev2 Spec: MSI and MSI-X Capability Structures
and PCI Express Capability List Register
Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0
Corresponding Section in PCIe Specification
Base Address Registers (Offset 10h/14h)
Secondary Latency Timer (Offset 1Bh)/Type 1
Configuration Space Header/ /Primary Bus Number
(Offset 18h)
Secondary Status Register (Offset 1Eh) / Type 1
Configuration Space Header
Type 1 Configuration Space Header
Prefetchable Memory Base/Limit (Offset 24h)
Type 1 Configuration Space Header
Type 1 Configuration Space Header
Type 1 Configuration Space Header
Type 1 Configuration Space Header
Type 1 Configuration Space Header
Bridge Control Register (Offset 3Eh)
MSI and MSI-X Capability Structures
MSI and MSI-X Capability Structures
MSI and MSI-X Capability Structures
MSI and MSI-X Capability Structures
MSI and MSI-X Capability Structures
MSI and MSI-X Capability Structures
MSI and MSI-X Capability Structures
PCI Power Management Capability Structure
PCI Power Management Capability Structure
PCI Express Capabilities Register / PCI Express
Capability List Register
Device Capabilities Register
Device Status Register/Device Control Register
Link Capabilities Register
Link Status Register/Link Control Register
Slot Capabilities Register
Slot Status Register/ Slot Control Register
Root Control Register
Root Status Register
December 2010 Altera Corporation
Chapter 6: Register Descriptions