IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 56

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–14
Avalon-MM Configuration
Table 3–6. Avalon Configuration Settings (Part 1 of 2)
PCI Express Compiler User Guide
PCIe Peripheral Mode
PCIe Peripheral Mode
(continued)
Address translation
table configuration
Avalon Clock Domain
Parameter
The Avalon Configuration page contains parameter settings for the PCI Express
Avalon-MM bridge, available only in the SOPC Builder design flow.
describes the parameters on the Avalon Configuration page.
Use PCIe core clock,
Use separate clock
Requester/Completer,
Completer-Only,
Completer-Only
single dword
Dynamic translation
table,
Fixed translation
table
Value
Allows you to specify one or two clock domains for your application
and the PCI Express IP core. The single clock domain is higher
performance because it avoids the clock crossing logic that separate
clock domains require.
Specifies if the PCI Express component is capable of sending requests
to the upstream PCI Express devices.
Sets Avalon-MM-to-PCI Express address translation scheme to
dynamic or fixed.
Use PCIe core clock—In this mode, the PCI Express IP core
provides a clock output, clk125_out, to be used as the single clock
for the PCI Express IP core and the SOPC Builder system.
Use separate clock—In this mode, the protocol layers of the PCI
Express IP core operate on an internally generated clock. The PCI
Express IP core exports clk125_out; however, this clock is not
visible to SOPC Builder and cannot drive SOPC Builder components.
The Avalon-MM bridge logic of the PCI Express IP core operates on
a different clock specified using SOPC Builder.
Requester/Completer—Enables the PCI Express IP core to send
request packets on the PCI Express TX link as well as receiving
request packets on the PCI Express RX link.
Completer-Only—In this mode, the PCI Express IP core can receive
requests, but cannot send requests to PCI Express devices.
However, it can transmit completion packets on the PCI Express TX
link. This mode removes the Avalon-MM TX slave port and thereby
reduces logic utilization. When selecting this option, you should also
select Low for the Desired performance for received completions
option on the Buffer Setup page to minimize the device resources
consumed. Completer-Only is only available in devices that include
hard IP implementation.
Dynamic translation table—Enables application software to write
the address translation table contents using the control register
access slave port. On-chip memory stores the table. Requires that
the Avalon-MM CRA Port be enabled. Use several address
translation table entries to avoid updating a table entry before
outstanding requests complete.
Fixed translation table—Configures the address translation table
contents to hardwired fixed values at the time of system generation.
Description
December 2010 Altera Corporation
Chapter 3: Parameter Settings
Avalon-MM Configuration
Table 3–6