IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 250

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–22
Table 15–21. DMA Control Register Setup for DMA Read
Root Port Design Example
PCI Express Compiler User Guide
DW0
DW1
DW2
DW3
0x0
0x14
0x18
0x1c
Offset in DMA Control
Registers (BAR2)
2. Sets up the chaining DMA descriptor header and starts the transfer data from the
3. Waits for the DMA read completion by polling the BFM share memory location
The design example includes the following primary components:
■
■
■
BFM shared memory to the endpoint memory by calling the procedure
dma_set_header which writes four dwords, DW0:DW3,
DMA read register module.
After writing the last dword of the Descriptor header (DW3), the DMA read starts
the three subsequent data transfers.
0x90c, where the DMA read engine is updating the value of the number of
completed descriptors. Calls the procedures rcmem_poll and msi_poll to
determine when the DMA read transfers have completed.
PCI Express IP core root port variation (<variation_name>.v).
VC0:1 Avalon-ST Interfaces (altpcietb_bfm_vc_intf_ast)—handles the transfer of
PCI Express requests and completions to and from the PCI Express IP core
variation using the Avalon-ST interface.
Root Port BFM tasks—contains the high-level tasks called by the test driver,
low-level tasks that request PCI Express transfers from altpcietb_bfm_vc_intf_ast,
the root port memory space, and simulation functions such as displaying
messages and stopping simulation.
3
0
0x900
2
Value
Number of descriptors and control bits as described in
page 15–14
BFM shared memory upper address value
BFM shared memory lower address value
Last descriptor written
Description
Chapter 15: Testbench and Design Example
(Table
December 2010 Altera Corporation
Table 15–5 on
15–21) into the
Root Port Design Example