IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 192

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

10–2
PCI Express Compiler User Guide
Figure 10–2
vector enable bit. A global application interrupt enable can also be implemented
instead of this per vector MSI.
Figure 10–2. Example Implementation of the MSI Handler Block
There are 32 possible MSI messages. The number of messages requested by a
particular component does not necessarily correspond to the number of messages
allocated. For example, in
allocated two. In this case, you must design the application layer to use only two
allocated messages.
Figure 10–3. MSI Request Example
Figure 10–4
in
is one clock cycle.
Figure
Vector 1
Vector 0
10–3. The minimum latency possible between app_msi_req and app_msi_ack
illustrates a possible implementation of the MSI handler block with a per
illustrates the interactions among MSI interrupt signals for the root port
app_int_sts0
app_int_sts1
8 Requested
2 Allocated
Endpoint
R/W
R/W
app_int_en0
app_int_en1
Figure
10–3, the endpoint requests eight MSIs but is only
Root Complex
Root
Port
app_msi_req0
app_msi_req1
Interrupt Register
app_int_sts
Interrupt
Block
Arbitration
MSI
December 2010 Altera Corporation
msi_enable & Master Enable
app_msi_ack
app_msi_req
CPU
Chapter 10: Interrupts
MSI Interrupts