TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 167
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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3.7.20
input or output. Resetting sets port U0 to U7 to input port and output latch to “0”.
data bus pin for LCD controller (LD16 to LD23) and as the SDCLK input function.
communication for debug mode (EO_TRGOUT). These functions are operated when it is
started in debug mode. In this case, PU7 can not be used as LD23 function.
Port U (PU0 to PU7)
Ports U0 to U7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port, PU0 to PU7 can also function as a
Setting in the corresponding bits of PUCR and PUFC enables the respective functions.
In addition to functioning as above function, PU7 can also function as the
LD16 to LD20, LD22,LD23
(on bit basis)
EO_TRGOUT
(on bit basis)
Output latch
Direction
Function
control
Reset
PUCR write
control
PUFC write
PU write
PU read
R
Figure 3.7.54 Port U0 to U4 , U6 , U7
A
B
Debug mode
C
Selector
Selector
S
S
92CF26A-166
A
B
PU0~PU4,PU6
PU7
(LD16 to LD20,LD22)
(LD23,EO_TRGOUT)
TMP92CF26A
2007-11-21
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