TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 443

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Receive IN token
Not receive SOF
Transmit data
Generate DATA PID
• Attach DATA0
• Confirm DATASIZE register
Confirm Token packet
Attach CRC
Figure 3.16.13 Control Flow in UDC (Isochronous transfer type (Transmission))
Not renewal frame number
loss data
OK
OK
OK
• Confirm STATUS register (status)
• PID
• Address
• Endpoint
• Transfer mode
• Error
Confirm Status
IDLE
IDLE
Error transaction
ReceiveSOF
• FRAME noread
• BANK shift
Shift FIFO BANKs
every receive SOF
Receive SOF
without transmitting data
Set LOST to FRAME register
Not renew FRAME number
Assert SOF
Error
92CF26A-442
BANK B transaction
BANK A transaction
Invalid
• Assert SOF
• Clear transmitting FIFO BANK A in preceding frame
• Clear DATASET register’s BANK A bit
• Set DATASET register’s BANK B bit
• Set STATUS to READY
• Wait data for transmitting next frame (BANK A)
• Assert SOF
• Clear transmitting FIFO BANK B in preceding
• Clear DATASET register’s BANK B bit
• Set DATASET register’s BANK A bit
• Set STATUS to READY
(Finish a write in previous frame)
frame
(Finish a write in previous frame)
Clear X condition (A)
Set FULL to STATUS
TMP92CF26A
2007-11-21