TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 228

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(b)
(c)
*AP: Auto Precharge
multiplex width is set by SDACR<SMUXW1:0>. Table 3.10.2 shows the relationship
between the multiplex width and low/column addresses.
When the LCDC accesses the SDRAM, the burst length is fixed to full page.
following conditions are satisfied:
Use SDBLS<SDBL5:0> to set the burst length for each HDMA channel.
Pin Name
92CF26A
In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The
When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single write.
The burst length can be selected for SDRAM read and write accesses by HDMA if the
In other cases, HDMA operation can only be performed in 1-word read/single write mode.
Address multiplex function
Burst length
•
•
A10
A11
A12
A13
A14
A15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
The HDMA transfer mode is an increment mode.
Transfers are made between the SDRAM and internal RAM or internal I/O.
<SMUXW> = 00
Type A
EA24
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A9
Table 3.10.2 Address Multiplex
<SMUXW> = 01
Row Address
SDRAM Access Cycle Address
92CF26A-227
Type B
EA24
EA25
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
<SMUXW> = 10
Type C
EA24
EA25
EA26
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
Column Address
Row Address
AP *
A10
A1
A2
A3
A4
A5
A6
A7
A8
A9
TMP92CF26A
2007-11-21