TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 753

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

TB1RG0H
TB1RG1H
TB1FFCR
TB1CP0H
TB1CP1H
TB1RG0L
TB1RG1L
TB1CP0L
TB1CP1L
Symbol
TB1MOD
TB1RUN
(15) 16-bit timer (2/2)
TMRB1
RUN
register
TMRB1
MODE
register
TMRB1
Flip-Flop
control
register
16 bit timer
register 0
low
16 bit timer
register 0
high
16 bit timer
register low
16 bit timer
register 1
high
Capture
register 0
low
Capture
register 0
high
Capture
register 1
low
Capture
register 1
high
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
119AH
119BH
119CH
119DH
119EH
1190H
1192H
1193H
1198H
1199H
119FH
RMW)
RMW)
RMW)
RMW)
RMW)
RMW)
Double
buffer
0: disable
1: enable
Always write “00”.
Always write “11”.
* Always read as “11”.
TB1RDE
R/W
7
0
−
0
−
1
R/W
W *
Always
write “0”.
R/W
6
−
0
−
0
−
1
92CF26A-752
Software
capture
control
0: Execute
1: Undefined
TB1FF0 inversion trigger
0: Disable trigger
1: Enable trigger
When
capture
UC12 to
TB1CP1H/L
TB1CP0I TB1CPM1 TB1CPM0
TB1CT1
W*
5
1
0
Capture timing
00: Disable
01: TB1IN0 ↑
10: TB1IN0 ↑ TB1IN0 ↓
When
capture
UC12 to
TB0CP0H/L
11: TA3OUT ↑
TB1C0T1 TB1E1T1 TB1E0T1 TB1FF0C1 TB1FF0C0
TA3OUT ↓
INT7 occurs at rising
edge
INT7 occurs at rising
edge
INT7 occurs at rising
edge
INT7 occurs at falling
edge
4
0
0
Undefined
Undefined
Undefined
Undefined
R/W
W
W
W
W
R
R
R
R
−
0
−
0
−
0
−
0
−
−
−
−
When UC12
matches
with
TB1RG1H/L
IDLE2
0: Stop
1: Operate
I2TB1
R/W
0
3
0
0
Control Up
counter
0:Clear
1:Clear
When UC12
matches
with
TB1RG0H/L
TMRB0
prescaler
0: Stop and clear
1: Run (Count up)
TB1PRUN
TB1CLE
Disable
Enable
R/W
R/W
0
0
2
0
TMRB1 source clock
00: TB1IN0 input
01: φ T1
10: φ T4
11: φ T16
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
* Always read as “11”.
TB1CLK1 TB1CLK0
TMP92CF26A
0
1
1
2007-11-21
W*
Up counter
(UC12)
TB1RUN
R/W
0
0
0
1