TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 359

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Master
Master
A
B
Internal
SCL output
Internal
SDA output
Internal
SCL output
Internal
SDA output
Accessed to
SBIDBR or SBICR2
(11)
(12)
(13)
<AL>
<MST>
<TRX>
internal SDA output on the rising edge of the SCL line. If the levels do not match,
arbitration is lost and SBISR<AL> is set to “1”.
When SBISR<AL> is set to “1”, SBISR<MST, TRX> are cleared to “00” and the mode is
switched to Slave Receiver Mode. Thus, clock output is stopped in data transfer after
setting <AL>=“1”.
data is written to SBICR2.
I2CAR<ALS> = “0”), when a GENERAL CALL is received, or when a slave address
matches the value set in I2CAR. When I2CAR<ALS> = “1”, SBISR<AAS> is set to “1”
after the first word of data has been received. SBISR<AAS> is cleared to “0” when
data is written to or read from the data buffer register SBIDBR.
8-bit received data is “0”, after a start condition). SBISR<AD0> is cleared to “0” when
a start condition or stop condition is detected on the bus.
SBISR<LRB>. In the acknowledge mode, immediately after an INTSBI interrupt
request is generated, an acknowledge signal is read by reading the contents of the
SBISR<LRB>.
Figure 3.15.13 Example of when TMP92CF26A is a master device B
Slave address match detection monitor
GENERAL CALL detection monitor
Last received bit monitor
The TMP92CF26A compares the levels on the bus’s SDA line with those of the
SBISR<AL> is cleared to “0” when data is written to or read from SBIDBR or when
SBISR<AAS> is set to “1” in Slave Mode, in Address Recognition Mode (i.e. when
SBISR<AD0> is set to “1” in Slave Mode, when a GENERAL CALL is received (all
The SDA line value stored at the rising edge of the SCL line is set to the
D7A
D7B
1
1
D6A
D6B
2
2
D5A
(D7A = D7B, D6A = D6B)
3
3
Keep Internal SDA output to high-level as losing arbitration
D4A
92CF26A-358
4
4
D3A
5
Stop the clock pulse
D2A
6
D1A
7
D0A
8
9
D7A’ D6A’ D5A’ D4A’
1
2
TMP92CF26A
3
2007-11-21
4