TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 411
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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USBREADY
(07E6H)
VDD
INTXX
PortXX
(Pull-up on/off)
Write signal
bit Symbol
Read/Write
Reset State
3.16.3.27 USBREADY Register
USBREADY (Bit0)
Note1: External pull-up resistor and control switch are needed with the TMP92CF26A.
Note2: The above setting is an example for when communication. A specific circuit is required to prevent cullent flow
0: Writing to descriptor RAM has finished.
1: Writing to descriptor RAM is enabled.
(However, writing to descriptor RAM is prohibited when connected to host.)
at connector detection , no-use, and no connection.
case, UDC disable detecting USB_RESET signal until USBREADY register is written
“0” after release of USB_RESET.
resistor is connected to host in OFF condition, this condition is equivalent condition
with USB_RESET signal by pull-down resistor on the host side. Therefore UDC is not
detected in USB_RESET until “0” is written to USBREADY register
This register informs finishing writing data to descriptor RAM on UDC.
After assigned data to descriptor RAM, write “0” to bit0.
Detect level of VDD signal from USB cable, and execute initialize sequence. In this
If the pull-up resistor on D+ signal is controlled by control signal, when pull-up
7
USB host
GND
6
15 kΩ
15 kΩ
92CF26A-410
5
Descriptor RAM access
Device ID RAM
Register in USB
R1 = 1.5 kΩ
4
R2
R3
3
VCC
VSS
PortXX
D+
D−
USBREADY registera access
2
TMP92CF26A
CPU
UDC
TMP92CF26A
1
2007-11-21
USBREADY
R/W
0
0
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