TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 454

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

5
6
7
it does not generate EPx_DATASET except in toggle transfer mode and Isochronous
transfer mode of interrupt.
“Initial” is that renew RESET, USB reset, Current_Config register. In detect error,
5 to 7 in shows the status register means that the endpoint is in special condition.
ISO transfer mode
Transfer modes other than ISO transfer
BUSY
STALL
INVALID
this.
renewed.
Below is the transfer condition for the previous frame. Receiving SOF renews
This is the result of the previous transfer. When transfer is finished, this is
Transfer finish normally
BUSY is generated only at endpoint of control transfer. If UDC transfer in control writes
transfer, when CPU has not finished enumeration transaction, and if it receives ID of status
stage from USB host, BUSY is set. STATUS is BUSY until CPU finishes enumeration
transaction and EP0 bit of EOP register is written 0 in UDC. If CPU enumeration transaction
finishes and EP0 bit of EOP register is written 0 and status stage from USB host finishes
normally, it displays READY.
Please refer to 5.2.3 in chapter 5.
STALL shows that endpoint is in STALL condition.
This condition is generated if it violates protocol or error in bus enumeration. To return
endpoint to normal transfer condition, USB device request is needed. This request returns
to normal condition. But control endpoint returns to normal condition by receiving SETUP
token. And it becomes to SETUP stage.
This condition shows condition that endpoint cannot be used. UDC sets condition that isn’t
designated in ENDPOINT to INVALID condition, and it ignores all tokens for this endpoint.
In initializing, this condition is always generated. When UDC detects hardware reset, it sets
all endpoints to INVALID condition. Next, if USB reset is received, endpoint 0 only is
renewed to READY. Other endpoints that are defined on disruptor are renewed if
SET_CONFIG request finishes normally.
Status stage finish
Finish normally
Detect anerror
Transfer error
Not transfer
Initial
Initial
92CF26A-453
OUT, SETUP
OUT (RX)
DATAIN
DATAIN
READY
READY
RXERR
READY
READY
RXERR
IN (TX)
READY
READY
READY
READY
READY
TXERR
TXERR
FULL
IN
TMP92CF26A
2007-11-21