TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 68

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.5
Interrupts
levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts
have a fixed priority level of 7, the highest level.
to the CPU. When more than one interrupt is generated simultaneously, the interrupt
controller sends the priority value of the interrupt with the highest priority to the CPU. (The
highest priority level is 7, the level used for non-maskable interrupts.)
CPU interrupt mask register <IFF2:0>. If the priority level of the interrupt is greater than or
equal to the value in the interrupt mask register, the CPU accepts the interrupt.
are processed irrespective of the value in <IFF2:0>.
(EI num sets <IFF2:0> to num). For example, the command EI3 enables the acceptance of all
non-maskable interrupts and of maskable interrupts whose priority level, as set in the
interrupt controller, is 3 or higher. The commands EI and EI0 enable the acceptance of all
non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence
both are equivalent to the command EI1).
instruction is used to disable all maskable interrupts (since the priority level for maskable
interrupts ranges from 0 to 6). The EI instruction takes effect as soon as it is executed.
micro DMA processing mode that can transfer data to internal/external memory and built-in
I/O, and HDMA processing mode. In micro DMA mode the CPU, and in HDMA mode the DMA
controller automatically transfers data in 1byte, 2byte or 4byte blocks. HDMA mode allows
transfer faster than Micro DMA mode.
HDMA processing is requested in software rather than by an interrupt. Figure 3.5.1 is a
flowchart showing overall interrupts processing.
Interrupts are controlled by the CPU Interrupt Mask Register <IFF2 to 0> (bits 12 to 14
of the Status Register) and by the built-in interrupt controller.
TMP92CF26A has a total of 56 interrupts divided into the following five types:
A fixed individual interrupt vector number is assigned to each interrupt source. Any one of six
When an interrupt is generated, the interrupt controller sends the priority of that interrupt
The CPU compares the interrupt priority level which it receives with the value held in the
However, software interrupts and illegal instruction interrupts generated by the CPU, and
The value in the interrupt mask register <IFF2:0> can be changed using the EI instruction
The DI instruction (Sets <IFF2:0> to 7) is exactly equivalent to the EI7 instruction. The DI
In addition to the general-purpose interrupt processing mode described above, there is also a
In addition, the TMP92CF26A also has a software start function in which micro DMA and
Interrupts generated by CPU: 9 sources
Internal interrupts: 38 sources
External interrupts: 9 sources
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Software interrupts: 8 sources
Illegal Instruction interrupt: 1 source
Internal I/O interrupts: 30 sources
Micro DMA Transfer End interrupts /HDMA Transfer End interrupts: 6 sources
Micro DMA Transfer End interrupts: 2 source
Interrupts on external pins (INT0 to INT7, INTKEY)
92CF26A-67
TMP92CF26A
2007-11-21