TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 308

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

A read-
modify-write
operation
cannot be
performed
TB0MOD
(1182H)
Bit symbol
Read/Write
Reset State
Function
TMRB0 source clock
Control clearing for up counter (UC10)
Capture/interrupt timing
Software capture
Always write “0”.
<TB0CPM1:0>
<TB0CLK1:0>
<TB0CP0I>
<TB0CLE>
7
−
0
R/W
6
−
0
Figure 3.13.4 Register for TMRB
00
01
10
11
00
01
10
11
TMRB0 Mode Register
0
1
0
1
Software
capture
control
0: Software
capture
1:Undefined
TB0CP0I
92CF26A-307
W*
5
1
TB0IN0 pin input
φT1
φT4
φT16
Disable
Enable clearing by match with TB0RG1H/L
Disable
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP1H/L at falling edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TA1OUT
Capture to TB0CP1H/L at falling edge of TA1OUT
The value of up counter is captured to TB0CP0H/L
Undefined
Capture timing
00:Disable
01:TB0IN0 ↑
10: TB0IN0 ↑ TB0IN0 ↓
11: TA1OUT ↑
TB0CPM1 TB0CPM0
INT6 occurs at
rising edge
INT6 occurs at
rising edge
INT6 occurs at
falling edge
TA1OUT ↓
INT6 occurs at rising
edge
4
0
Capture control
3
0
Control
Up counter
0:Disable
1:Enable
TB0CLE
R/W
2
0
TMRB0 source clock
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
TB0CLK1
INT6 occurs at the rising
edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0
1
0
INT6 control
TMP92CF26A
TB0CLK0
2007-11-21
0
0