TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 90

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Interrupt REQ
3.6.1
DMAnV
DMAR
DMAB
DMASEL
→DMAC or micro DMA request
→DMAC or micro DMA soft start
→Micro DMA burst setting
→DMAC or micro DMA select
INTC (Interrupt Controller)
source setting
setting
setting
Note: “n” denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5).
Block Diagram
SDRAM Controller
Figure 3.6.1 shows an overall block diagram for the DMAC.
7
0
Micro DMA REQ,
Micro DMA Channel
DMA REQ,
DMA Channel
Micro DMA ACK,
INTTCn
DMA ACK,
INTDMAn
Bus REQ
Figure 3.6.1 Overall Block Diagram
Bus ACK
HDMACAn
HDMACBn
92CF26A-89
HDMAE
HDMATR
HDMASn
HDMADn
HDMAMn
LCD Controller
DMACn
→Micro DMA destination address setting
DMASn
DMADn
DMAMn
DMAC
CPU
→DMA destination address setting
→DMA maximum bus occupancy
time setting, mode setting
→Micro DMA transfer count setting
→Micro DMA source address setting
→Micro DMA mode setting
→DMA operation enable/disable
→DMA transfer count B setting
→DMA source address setting
→DMA transfer count A setting
→DMA mode setting
31
31
15
15
7
7
Address Bus
0
0
0
0
0
0
Address Bus
Data Bus
State
Address Bus
Data Bus
State
Address Bus
Data Bus
State
State
Bus
Multiplexer
Address Bus
Data Bus
State
Address Bus
Data Bus
State
TMP92CF26A
2007-11-21
Source Memory, I/O
Destination Memory, I/O