TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 37

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Status of Received Interrupt
RESET
INTWDT
INT0 to 5 (Note1)
INTKEY
INTUSB
INT6 to 7(PORT) (Note1)
INT6 to 7(TMRB)
INTALM, INTRTC
INTTA0 to 7, INTTP0
INTTB00 to 01, INTTB10 to 11
INTRX,INTTX, INTSBI
INTI2S0 to 1, INTLCD,
INTAD, INTADHP
INTSPIRX,INTSPITX
INTRSC, INTRDY
INTDMA0 to 5
HALT mode
× : Cannot be used to release the halt mode.
− : The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. This
*1: Release of the HALT mode is executed after warm-up time has elapsed.
*2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode, allowing for the construction of low
Note: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level
: After clearing the Halt mode, CPU starts interrupt processing.
: After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT instruction.
combination is not available.
power dissipation systems. However, the method of use is limited as below.
• Shift to IDLE1 mode :
• Release from IDLE1 mode :
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state )
Release Halt state by INT_RESUME or INT_CLKON request (release SUSPEND request)
Release Halt state by INT_URST_STR or INT_URST_END request(RESET request)
Table 3.3.5 Source of Halt state clearance and Halt clearance operation
H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly
started.
(interrupt level) ≥ (interrupt mask)
IDLE2
Interrupt Enabled
92CF26A-36
IDLE1
×
×
×
*2
Reset initializes the LSI
STOP
×
×
×
×
×
*1
*1
(interrupt level) < (interrupt mask)
IDLE2
−
×
×
Interrupt Disabled
IDLE1
−
×
×
*2
TMP92CF26A
2007-11-21
STOP
−
×
×
×
×
*1
*1