TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 235
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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SRS2 SRS1 SRS0
SDRCR<SRS2:0>
0
0
0
0
1
1
1
1
(6) Refresh control
0
0
1
1
0
0
1
1
(a) Auto Refresh
Note: A system reset disables the Auto Refresh function.
Note1: Set the interval of Auto Refresh as below table for your reference.
Note2: Take care SDRAM specification and CPU operation speed, please.
Note: Above gray zone is prohibited to set. SDRAM request: 4096 times per 64mS.
The TMP92CF26A supports two kinds of refresh commands: Auto Refresh and Self Refresh.
intervals specified by SDRCR<SRS2:0>. The Auto Refresh interval can be specified in a
range of 47 states to 1248 states (0.78 μs to 20.8 μs at f
command is being executed. Figure 3.10.6 shows the Auto Refresh cycle timing, and Table
3.10.3 shows the Auto Refresh interval settings. The Auto Refresh function cannot be used
in IDLE1 and STOP modes. In these modes, use the Self Refresh function to be explained
next.
0
1
0
1
0
1
0
1
When SDRCR<SRC> is set to “1”, the Auto Refresh command is automatically issued at
The CPU operation (instruction fetch and execution) is halted while the Auto Refresh
interval
state
1248
156
312
468
624
936
47
78
Table 3.10.3 System clock speed & auto refresh interval
1248.0 624.0
156.0
312.0
468.0
624.0
936.0
47.0
78.0
1
Figure 3.10.6 Auto Refresh Cycle Timing
156.0
234.0
312.0
468.0
23.5
39.0
78.0
2
SDLUDQM
SDLLDQM
SDRAS
SDCAS
SDWE
SDCKE
SDCLK
15.67
104.0
156.0
208.0
312.0
416.0
SDCS
26.0
52.0
3
92CF26A-234
11.75
117.0
156.0
234.0
312.0
19.5
39.0
78.0
4
Frequency: system clock [ MHz ]
Time: auto refresh interval [ μS ]
104.0
156.0
208.0
7.83
13.0
26.0
52.0
78.0
6
Auto Refresh
2 states
117.0
156.0
5.88
9.75
19.5
39.0
58.5
78.0
8
15.60
124.8
4.70
7.80
31.2
46.8
62.4
93.6
10
SYS
= 60 MHz).
15.60
2.35
23.4
31.2
46.8
62.4
20
3.9
7.8
15.60
1.57
2.60
5.20
10.4
20.8
31.2
41.6
30
15.60
1.18
1.95
3.90
7.80
11.7
23.4
31.2
40
TMP92CF26A
15.60
2007-11-21
0.78
1.30
2.60
5.20
7.80
10.4
20.8
60
11.70
15.60
0.59
0.98
1.95
3.90
5.85
7.80
80
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