TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 429

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(a-2) Receiving bulk mode
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Below is the transaction format for receiving bulk transfer type.
Control flow
Below is the control-flow when the UDC receive an IN token.
UDC finishes normally.
This flow is shown in Figure 3.16.8.
1.
2. Condition of status register is confirmed.
3. Data packet is received.
4.
5. If CRC is compared with toggle and it finishes normally, ACK handshake is
Token: OUT
Data: DATA0/DATA1
Handshake: ACK, NAK, STALL
• INVALID condition: State returns to IDLE.
• STALL condition: When dataphase finishes, stall handshake is returned,
FIFO condition is confirmed, if data number of 1 packet is not prepared, present
transferred data is canceled, NAK handshake is returned after dataphase, and
the state returns to IDLE.
• Set transfer data number to DATASIZE register.
• Set DATASET register.
• Renew toggle bit, and prepare for next.
• Set STATUS to READY.
The token packet is received and the address endpoint number error is
confirmed, and it checks whether the relevant endpoint transfer mode
corresponds with the OUT token. If it does not correspond, the state returns to
IDLE.
Data is transferred from SIE of internal UDC to FIFO. At this point, it
confirms transferred data number and if there is more than the maximum
payload size of each endpoint, STATUS becomes to STALL and the state
returns to IDLE. ACK handshake does not return.
transferred CRC. If they do not correspond, STATUS is set to RX_ERR and the
state returns to IDLE. At this point ACK is not returned.
After retry, when next data is received normally, STATUS changes to DATIN.
If the data toggle does not correspond, it is judged not to have taken ACK in
the last loading the current loading is regarded as a retry of the last loading
and data is canceled. Set STATUS as RX_ERR, return to host and return to
IDLE. FIFO address pointer returns and the next data can be received.
returned.
Below is the process in the UDC.
After last data is transferred,
92CF26A-428
the state returns to IDLE, and data is canceled.
the counted CRC is compared with the
TMP92CF26A
2007-11-21