TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 95

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

HDMAMn
bit Symbol
Read/Write
Reset State
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note 1: Read-modify-write instructions can be used on all these registers.
Note 2: INC: Post-increment
(5) HDMAMn (DMA Transfer Mode Setting Register)
Dec: Post-decrement
I/O: Fixed memory address
MEM: Memory address to be incremented or decremented
The HDMAMn register is used to set the DMA transfer mode.
HDMAM0 to HDMAM5 have the same configuration.
Transfer mode
7
HDMAM0
HDMAM1
HDMAM2
HDMAM3
HDMAM4
HDMAM5
(090CH)
(091CH)
(092CH)
(093CH)
(094CH)
(095CH)
[7:0]
6
Figure3.6.6 HDMAMn Register
HDMAMn Register
5
92CF26A-94
100: Source/destination INC
101: Source/destination DEC
110: Source/destination fixed
DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
111: Reserved
DnM4
4
0
(MEM → MEM)
(MEM → MEM)
(I/O→ I/O)
DnM3
3
0
DnM2
(Note 2)
R/W
2
0
Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved
DnM1
1
0
TMP92CF26A
DnM0
2007-11-21
0
0