TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 77

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.5.2
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
flip-flop), an interrupt priority setting register and a micro DMA /HDMA start vector
register. The interrupt request flag latches interrupt requests from the peripherals.
the channel vector of an interrupt it has received, when the CPU receives a micro DMA
request (when micro DMA is set), when the CPU receives a HDMA request (when HDMA is
set), when a micro DMA burst transfer is terminated, and when an instruction that clears
the interrupt for that channel is executed (by writing a micro DMA start vector to the
INTCLR register).
priority to the interrupt priority setting register (e.g., INTE0 or INTE12). Six interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source.
simultaneously, the default priority (The interrupt with the lowest priority or, in other
words, the interrupt with the lowest vector value) is used to determine which interrupt
request is accepted first. The 3rd and 7th bits of the interrupt priority setting register
indicate the state of the interrupt request flag and thus whether an interrupt request for a
given channel has occurred.
interrupt request for the interrupt with the highest priority and the interrupt’s vector
address to the CPU. The CPU compares the mask value set in <IFF2:0> of the status
register (SR) with the priority level of the requested interrupt; if the latter is higher, the
interrupt is accepted. Then the CPU sets SR<IFF2:0> to the priority level of the accepted
interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests
with a priority value equal to or higher than the value set in SR<IFF2:0> (e.g., interrupts
with a priority higher than the interrupt being processed) will be accepted.
When interrupt processing has been completed (e.g., after execution of a RETI instruction),
the CPU restores to SR<IFF2:0> the priority value which was saved on the stack before the
interrupt was generated.
DMA /HDMA start vector. Writing the start vector of the interrupt source for the micro
DMA or /HDMA processing (See Table), enables the corresponding interrupt to be processed
by micro DMA or HDMA processing. The values must be set in the micro DMA parameter
registers (e.g., DMAS and DMAD) or HDMA parameter registers (e.g., HDMAS, and
HDMAD) prior to micro DMA or HDMA processing.
Interrupt Controller Operation
The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the
For each of the 59 interrupts channels there is an interrupt request flag (consisting of a
The flag is cleared to “0” in the following cases: when a reset occurs, when the CPU reads
If more than one interrupt request with a given priority level are generated
If several interrupts are generated simultaneously, the interrupt controller sends the
The interrupt controller also includes eight registers which are used to store the micro
An interrupt priority can be set independently for each interrupt source by writing the
92CF26A-76
TMP92CF26A
2007-11-21