TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 185
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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AM1
(2) Memory Access Operations After Reset
0
0
1
1
Note: The memory that is used for booting after reset must be either NOR-Flash or Masked-ROM. NAND-Flash
determined by the AM1 and AM0 pins. The settings of the AM1 and AM0 pins and their
corresponding operation modes are as follows:
specified by the <BnBUS1:BnBUS0> bits of the control registers at any other timing.
automatically becomes effective. (The B2CSH<B2E> bit is set to 1 upon reset.).Then, the
AM1 and AM0 values that specify the data bus width are loaded into the data bus width
specification bits of the control register for the CS2 space.At the same time, the address
range ebtween 000000H and FFFFFFH is defined as the CS2 space. (The B2CSH<B2M>
is cleared to 0.)
BnCSL registers are also set up. The BnCSH<BnE> must be set to 1 to enable these
settings.
After reset, external memory is accessed using the initial data bus width that is
The values of AM1 and AM0 are effective only upon reset. The data bus width is
Upon reset, only the control registers (B2CSH and B2CSL) for the CS2 space
Then, the address spaces are configured by MSARn and MAMRn. The BnCSH and
SDRAM cannot be used.
AM0
0
1
0
1
Boots from external memory using a16-bit data bus
Boots from the on-chip boot ROM (32-bit on-chip-MROM )
92CF26A-184
Don’t use this setting
Don’t use this setting
Start Mode
(Note)
TMP92CF26A
2007-11-21
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