TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 233
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Internal system clock
Internal dat bus
Internal system
Internal data bus
COMMAND
COMMAND
(4) Read data shift function
D15-D0
SDCLK
A15-A0
D15-D0
SDCLK
A15-A0
clock
SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in the
next state. When this read data shift function is used, the read cycle requires additional one
state. The write cycle is not affected. The timing waveforms for various cases are shown below.
If the AC specifications of the SDRAM cannot be satisfied when data is read from the
(a) 1-word read, the read data shift function disabled (SDACR<SRCS> = “0”)
(b) 1-word read, the read data shift function enabled (SDACR<SRDS> = “1”,
NOP
<SRDSCK>= “0”)
NOP
Row Address
Row Address
ACTIVE
ACTIVE
READ
READ
ColumnAddress
92CF26A-232
External data latch
ColumnAddress
NOP
NOP
DIN1
DIN1
CPU data read
NOP
NOP
DIN1
Row Address
DIN1
CPU data read
ACTIVE
NOP
Row Address
ACTIVE
READ
Address
Column
TMP92CF26A
2007-11-21
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