TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 491

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(1) UNIT transmission
(2) Sequential transmission
(3) UNIT reception
(4) Sequential reception
(5) UNIT transmission and
(6)Sequential transmission
Operatiing Mode
reception
and reception
x: Don’t care
(k) RXE
[Data Transmission/Reception Modes]
This SPI Controller supports six operating modes as listed below.
These are specified by the FDPXE, RXMOD, RXE, TXMOD, TXE bits.
UNIT-size data.
more UNIT data is additionally received.
the 32-byte FIFO buffer becomes full. The state of this bit can be changed even during
the data reception. If this bit is cleared to 0 during a data reception, the reception is
stopped after completing the reception of the UNIT data currently being received.
In the UNIT–mode reception, writing a 1 to this bit enables the reception of only one
When reading the receive data register (SPIRD) while this bit is kept enabled, one
In Sequential mode, writing a 1 to this bit enables the sequential data reception until
<FDPXE>
0
0
0
0
1
1
Table 3.17.2 Data Transmission Reception Modes
<TXMOD>
0
1
x
x
0
1
Bit Settings
<TXE>
92CF26A-490
1
1
x
1
1
x
<RXMOD>
x
x
0
1
0
1
<RXE>
1
1
1
1
x
x
Transmit the SPITD data per UNIT
Transmit the FIFO data sequentially
Receive only one UNIT-size data
Automatically receive data if FIFO buffer
has any empty space
Transmit/receive one UNIT-size data with
the addresses of transmit/receive data
aligned on UNIT-size boundaries
Transmit/receive data sequentially with the
addresses of transmit/receive data aligned
on UNIT-size boundaries
Description
TMP92CF26A
2007-11-21