TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 537
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Reference LHSYNC
(Delay=0)
Note 1: The horizontal back porch must be set so that “data transfer” plus “LCP0 × 2 clocks” are completed within one
Note 2: The vertical back porch must have a minimum of one dummy clock.
• Insertion of dummy clocks
(*) TFT driver
(*) STN driver
period of the reference clock LHSYNC (with 0 delay), as defined by the following equation:
Delay time (LLOAD) + number of data transfer times + 2 < LHSYNC (LCP0 pulse count)
module). Refer to the specifications of the TFT driver (LCD module) to be used.
the horizontal back porch. If the desired refresh rate cannot be obtained by the
horizontal back porch, it can be further adjusted by the vertical back porch. For details,
refer to the setting example to be described later in this section.
(with delay)
horizontal synchronization signal (LHSYNC), and vertical synchronization signal
(LVSYNC) on the LCD panel.
in setting LCDHSP<LH15:0> and LCDVSP<LV9:0> explained earlier.
LVSYNC
LHSYNC
LD23-0
The recommended number of dummy clocks is specified by each TFT driver (or LCD
For an STN driver, the refresh rate can be set accurately by adjusting the value of
LCP0
The above is a conceptual diagram showing the data (LD23-0), shift clock (LCP0),
The front porch and back porch as shown above should be taken into consideration
Horizontal Front
Porch
92CF26A-536
Vertical Front Porch
Vertical back Porch
Note: At least two LCP0 pulses
must be inserted.
Horizontal back
TMP92CF26A
Porch
2007-11-21
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