TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 204

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(2) Setting up the NAND flash area
Note 1: In the above setting, 296 Kbytes out of the memory area for the CS3 (000000H to 049FFFH) cannot be used.
Note 2: The 16-byte area (001FF0H to 001FFFH) is predefined asNAND Flash area as shown below regardless of
000000H to 3FFFFFH, the following description is provided for such condition.In this case,
the NAND flash area overlaps with the CS3 space. However, the
by setting the BROMCR<CSDIS> bit to 1. Likewise, the
CSXA
(NAND-Flash area specification)
Figure 3.8.8 shows a memory map for the NAND flash memory.
Since it is recommended that the CS3 space be located in the memory area from
which CS space is selected. Therefore, the setting of the CS3 space does not affect the NAND flash area.
1. Bus width
2. Wait control : Specified by NDFMCR<SPLW1:SPLW0> and NDFMCR<SPHW1:SPHW0> in
through
001FF0H
002000H
021FFFH
04A000H
000000H
200000H
400000H
Figure 3.8.8 Recommended CS3 Space Assignment
046000H
: Specified by NDFMCR1<BUSW> in the NAND Flash controller.
CSXB
the NAND Flash controller
pins and the
Internal Back UP RAM
Internal RAM
COMMON X
(144Kbytes)
NAND flash
(16 Kbytes)
Internal I/O
(2 Mbytes)
(2 Mbytes)
(16 bytes)
LOCAL X
92CF26A-203
CSZA
through
CSZD
CS3 area setting
000000H to 3FFFFFH (4 Mbytes)
pins are not asserted either.
CS
0
CS
through
All CS pins become to unactibe
by BROMCR<CSDIS> = ”1”
3
pin is not asserted
TMP92CF26A
CS
2007-11-21
3
pins, the